1. Field of the Invention
The invention relates to a method for machining a semiconductor wafer which is guided in a cutout in a carrier while a thickness of the semiconductor wafer is being reduced to a target thickness by material being removed from a front surface and a back surface of the semiconductor wafer simultaneously. A method of this type is used in particular for the double side polishing and lapping of semiconductor wafers. A carrier is used to hold and guide at least one semiconductor wafer during machining. To protect the semiconductor wafer, the cutout of the carrier in which the semiconductor wafer lies during machining is lined with an inlay. A carrier of this type is formed by a carrier body and the at least one inlay.
2. Background Art
According to U.S. Pat. No. 6,454,635, during machining the semiconductor wafer acquires a bead-like thickened portion in the edge region when the thickness of the inlay, as a result of wear, becomes less than the thickness of the carrier body. US-2004/0235401 includes the description of a carrier, the inlay of which is at least 20 μm thicker than the thickness of the carrier body. This is intended to prevent wear to the carrier body from releasing metals during the machining of the semiconductor wafer, which would contaminate the semiconductor wafer.
JP-05-177539 A proposes a method for the double side polishing of semiconductor wafers, according to which the thickness t of the semiconductor wafer to be machined, the thickness T of the carrier and the depth of penetration x of the semiconductor wafer into the polishing cloth are matched to one another according to the inequality T−2x<t<T+2x. The method can be used, inter alia, to produce semiconductor wafers which are concave in cross section and in which a particularly flat front surface can be generated by subsequent single side polishing.
It is desirable for the demands imposed on the flatness of the front surface of a semiconductor wafer as far as possible also to be satisfied in the edge region of the semiconductor wafer, so that this region can also be used to construct electronic components.
The local flatness on the front surface of a semiconductor wafer is generally specified by the SFQRmax value. For this purpose, the area of the front surface is divided into sites, taking into account an edge exclusion, and the positive and negative deviation from a reference plane is determined, the reference plane being determined for each site by error square minimization. The SFQRmax value (Site Frontside Site-Least-Squares Range) indicates the deviation which is not exceeded in 100% of the sites.